Storage latches, such as a data latch (or “D latch”), are implemented using various circuit layouts. Storage latches can be used to build counting circuitry and storage circuits for numbers. In fact, integrated circuits containing thousands of storage latch components are often used as data-storage (or memory) devices in computers. The value of a latch and associated circuitry output depends on the past history of the inputs as well as the current values of the inputs, thus, the particular sequence of inputs matters.
Some examples of storage latch uses include read-only applications and integrated circuit testing. For example, scan based test methodology for testing faults, DC type testing, and basic testing of shorts may use storage latches. To facilitate this testing methodology, a number of storage latches may be necessary, with some integrated circuits requiring thousands of storage latches.
FIG. 1 illustrates a conventional storage latch design 100. The circuit includes a data input 110, a clock input 120, a flip-flop formed by NAND gates 140 and 160, and enabling gates 130 and 150. It is desirable for the flip-flop to respond to the data input only at certain times and to ignore the data input at all other times, thus the inclusion of enabling gates 130 and 150. Enabling gate 130 passes D and enabling gate 150 passes D(NOT) (i.e. inverted version of D) to the inputs of the flip-flop only when the clock input (i.e. enabling input) is active (i.e. a logic one).
The D input is sampled during the occurrence of a clock pulse. If it is a logic 1, the output Q 170 of the flip-flop is set to a logic 1 (if D is a logic 1, then the output of enabling NAND gate 130 is a logic 0, the output of enabling NAND gate 150 is a logic 1, the output Q 170 of NAND gate 140 is a logic 1 and the output Q(NOT) 180 of NAND gate 160 is a logic 0). If D is a logic 0, the output Q 170 of the flip-flop is set to 0. When the clock input 120 is not active, the flip-flop remains in its previous state (i.e. either a logic 1 or logic 0) indefinitely because of the cross-couple nature of the flip-flop device, thus forming a memory element. Thus, a binary digit can be stored in the D latch and the device can be used as a memory element. The memory element can be set to a logic 1 or reset to a logic 0 by appropriate pulses on the input and clock lines. To store an n-bit binary number would require n flip-flops.
Data storage circuits, such as that described in FIG. 1, may be used for testing within a more complex integrated circuit. Data storage latches may be arranged together, such as in parallel, so that one latch feeds into another latch. During one clock event, data can be captured in the first latch. During a second clock event, the data may be transferred to the next latch. This can be continued for as many latches that exist in the integrated circuit.
During the testing of an integrated circuit, test patterns are loaded into latches, typically one bit at a time. The test patterns are clocked through the latches and excite the appropriate circuitry, thereby facilitating excitation and observation of an integrated circuit (IC).
Conventional data latches are implemented using standard circuit methodologies such as CMOS transistor-based logic blocks such as NAND gates, AND gates, invertors, and the like. However, such implementation may involve thousands of latches, and potentially hundreds of thousands of transistors. Thus, conventional data storage latches take up a lot of room in an integrated circuit (i.e. silicon area), as well as use up large amounts of power and hinder performance.
As the size of a transistor is reduced, sub-threshold leakage may increase. Even when the transistor is inactive and not switching, there may still be an amount of leakage current from the source of the transistor to its drain. The amount of leakage becomes noticeable based on the thousands of potential latches that may be used. For example, in CMOS, this is due to the nature of CMOS circuit design, and processes. Thus, each latch used in an IC adds to the total dynamic and static power consumption of the IC. This power consumption becomes nontrivial as transistor sizes continue to decrease and the number of latches incorporated in ICs increase.
Transistors also include an inherent delay associated with the transmission of signals due to a number of parasitic capacitances inherent in transistor devices. Transistors in conventional data latches may cause an additional delay within the integrated circuit to which the data latches are attached. This additional delay may adversely impact the overall performance of the integrated circuit. In particular, at high speeds, such as is the gigahertz range, the transistor delay may begin to significantly deteriorate the tolerance of the design.
FIG. 2 illustrates a micro-electromechanical switch (also referred to as a MEMS or as a MEMs switch). An exemplary double-pole MEMs switch 200 is integrated into standard CMOS processes. The first pole 210 is activated by first control electrode 220 and the second pole 230 is activated by second control electrode 240. It would be desirable to replace conventional transistor-based data latches with MEMs-based data latches. Since MEMs switches are fabricated in the metal wiring layers of an integrated circuit and exhibit more ideal switch characteristics (extremely low leakage), a MEMs-based data latch would consume no silicon in an integrated circuit, would eliminate power consumption associated with transistor-based latches and would improve performance by eliminating the inherent delay associated with conventional CMOS transistors.